FIG. 1 is a schematic diagram of a conventional input protection circuit for a MOS device. The input protection circuit 300 comprises a resistor (R) 300A connected in series between an input terminal 100 and internal circuitry 200, and a MOS transistor 300B whose drain is connected to one end of the resistor 300A and whose source and gate are respectively connected to ground (Vss).
FIG. 2 is a cross-section profile including the resistor 300A, a connection C of the resistor 300A and the drain of the MOS transistor 300B and part of the internal circuitry 200.
An n-type doped region 2 and an n-type doped region 3 are formed respectively on the surface of a p-type semiconductor substrate 1, such as a silicon substrate. The n-type doped region 2 makes the drain of the MOS transistor 300B in FIG. 1. The n-type doped region 3 makes part of the internal circuitry 200. Plates 4a, 4b and 4c of polycrystalline silicon films are respectively formed on the p-type semiconductor substrate, isolated by an insulator 1a, such as a silicon dioxide film, in between. Each of the plates 4a, 4b and 4c is typically connected to a power source, such as ground (Vss), which makes a field isolation region between the input protection circuit 300 and the internal circuitry 200. As a result, the surface of the p-type substrate 1 directly beneath the plates 4a, 4b and 4c is prevented from inverting, and thus the n-type doped region 2 and the n-type doped region 3 are electrically isolated.
Over the plates 4a, 4b and 4c is an interlayer insulator 5, such as a silicon dioxide film which can be made by chemical vapor deposition. The interlayer insulator 5 isolates a polycrystalline silicon layer 6 formed directly above the plate 4a. The polycrystalline silicon layer 6 makes the resistor 300A. Each of the electrode wiring layers 7 and 8 of aluminum is electrically connected to the polycrystalline silicon layer 6 via contacts 7a and 9a of the interlayer insulator 5, respectively. The electrode wiring layer 8 is electrically connected to the n-type doped region 2 via the contact 8b of the interlayer insulator 5. To the n-type doped region 3 for the internal circuitry 200, an electrode wiring layer 9 which is of aluminum, too, is electrically connected via contact 9a of the interlayer insulator 5.
The conventional input protection circuit 300 with the structure described above may not have any problem when used in a system with a supply voltage of 5 V wherein the voltage inputted is usually 0 to 5 V. However, the problem described below may result when the circuit is used in a system where an abnormal current may occur such as the one shown in FIG. 3, that is, a big undershooting of an input waveform (Vin) becoming lower than the ground potential (Vss=0).
FIG. 4 shows the relationship between the input current and the input voltage applied to the input terminal 100 shown in FIG. 1. As shown in FIG. 4, a negative input current increases when the input voltage (Vin) becomes lower than the ground potential (Vss=0). This is due to a parasitic MOS transistor 10 shown in FIG. 2, formed with the n-type doped region 2 for a source, the n-typed doped region 3 for a drain and the plate 4b for a gate thereof. On application of a voltage exceeding the threshold voltage (Vth) of the parasitic MOS transistor 10, which is typically 2 to 10 V, the parasitic MOS transistor 10 turns on to pass a current between the n-type doped regions 2 and 3. The current makes the n-typed doped region 3, part of the internal circuitry 200, change to a negative because of the negative applied voltage. Thus, malfunctions result.
The present invention serves to solve the problem described above. It is an object of the invention to provide a MOS device and the method of manufacturing the same, to suppress generation of a parasitic MOS transistor and thereby to prevent malfunctions due to abnormal currents without any additional step of manufacturing process.